A. Field of the Invention
This invention relates to logic systems and more particularly to synchronous differential logic circuits for very large scale integrated systems which operate at very high frequency.
B. Background Art
Advanced CMOS fabrication technologies are capable of producing VLSI systems comprising millions of transistors and wires. However, CMOS has yet to be exploited to its full potential for manufacturing not only complex but also high performance VLSI systems.
Efforts toward improving VLSI system performance have proceed on all levels including improvements in architecture and logic circuits. At the architectural level the press for increased performance has led to the development of two forms of concurrency--parallelism and pipelining. Parallelism emphasizes concurrency by replicating a hardware structure many times. Pipelining takes the approach of providing combinational logic structures with clocked data latches to hold intermediary results so that the processing of one data set can be performed concurrently with the processing of other data sets. As the number of logic levels interposed between successive clocked latches decreases, the pipelined system could be operated at higher clock frequencies and thus the amount of work performed concurrently could be increased. However, the implementation of high performance maximally pipelined systems has not been commercially viable because of the relatively high incremental cost of data latches.
At the circuit level, the development of logic gates having shorter switching times, hence permitting operation of VLSI systems at higher clock frequencies has been a constant goal. The major improvements in logic circuits performance has been due to advances in CMOS fabrication technologies which produced transistors with higher gain per chip area and interconnections with less parasitic capacitance and resistance between logic circuits. However, little improvement in circuit performance has come from new types of CMOS logic gates.
There are two types of logic circuits which are used in digital VLSI systems, i.e., single-ended and differential. Single-ended CMOS logic circuits are characterized by having a single current path between a power supply bus and ground and by the use of a single signal conductor to connect the output of one gate to the input of another gate. During the transition period from one logic level to the opposite one, single-ended CMOS circuits are known to generate a significant amount of switching noise. The problem is further exacerbated by an occasional simultaneous switching of a group of single-ended off-chip drivers which alter the current demand on the power supply thus causing an instantaneous voltage collapse. This type of noise which depends on the data being processed by the VLSI system is difficult or impossible to filter out due to its low frequency of occurrence. Moreover, switching noise can affect the correct operation of other gates and consequently limits the upper clock frequency of such systems.
A differential logic gate has two current paths between the power supply buses. One current path produces a logic value at one output while, simultaneously, the other current path produces its logic complement at the other output. A differential logic system uses two wires for each signal connected from a differential output of one gate to a differential input of another gate. Logic values in a differential logic system are defined as the algebraic voltage difference between the two complementary signal wires. Differential circuits could be less sensitive to noise, signal line voltage drops, and power supply variations, than single-ended circuits.
A differential logic gate comprises a differential switch and a load circuit. A plurality of differential inputs are connected to the differential switch which provides a path to ground, only on one of its two outputs, as a function of the logic values of the inputs. (The differential switch is a single pole double throw switch implemented with transistors and controlled by one or more differential inputs.) The load circuit senses the current into the outputs of the differential switch and produces a given output signal at a first output node and a second output signal, which is the complement of that of the given output signal, at a second output node.
There is a class of differential circuits that use load circuits which are controlled by a clock. In these synchronous circuits, both differential outputs are precharged in one phase of the clock to a given voltage and in a second phase of the clock, the inputs are evaluated to provide a logic value at the outputs which is a Boolean function of the inputs.
Synchronous differential logic circuits suitable for implementing pipelined VLSI systems have been known in the prior art. Applicants believe that the invention, as set forth herein, has many significant advantages over the circuits of the prior art, especially when ones purpose is to produce useful maximally pipelined systems which are to operate at a much higher frequency than the prior art system. Although none of the prior art known to the applicants teaches or suggests applicants' invention, the closet reference is described as follows.
A synchronous, latched, differential CMOS logic circuit was described by T. A. Grotjohn and B. Hoefflinger in an article entitled "Sample-Set Differential Logic (SSDL) for Complex High-Speed VLSI," in Journal of Solid-State Circuits, vol. SC-21, No. 2, pp. 367-369, April 1986.